Programmable devices are general-purpose integrated circuits that can be configured for a wide variety of applications. Such programmable devices have two basic versions, mask programmable devices, which are programmed only by a manufacturer, and field programmable devices, which are programmable by the end user. In addition, programmable devices can be further categorized as programmable memory devices or programmable logic devices. Programmable memory devices include programmable read only memory (PROM), erasable programmable read only memory (EPROM) and electronically erasable programmable read only memory (EEPROM). Programmable logic devices include programmable logic array (PLA) devices, programmable array logic (PAL) devices, erasable programmable logic devices (EPLD) devices, complex programmable logic devices (CPLD), programmable gate arrays (PISA), application specific integrated circuits (ASIC).
As chip capacity continues to increase significantly, the use of field programmable gate arrays (FPGAs) is quickly replacing the use of application specific integrated circuits (ASICs). An ASIC is a specialized integrated circuit that is designed and mask programmed for a particular application such as a specialized microprocessor. With the shrinkage in integrated circuit design rules, FPGAS, which are user programmable, achieve almost the gate density of factory programmed ASICs. This high gate density has contributed immensely to the popularity of FPGAs. FPGAs typically include user configurable input/output blocks (IOBs), and programmable logic blocks, and configurable interconnect lines, and switching capability for interconnecting the lines and programming the blocks.
The advancement of computer chip technology has also resulted in the development of embedded processors and controllers. An embedded processor or controller can be a microprocessor or microcontroller circuit that has been integrated into an electronic device as opposed to being built as a standalone module or “plug in card.” Advancement of FPGA technology has led to the development of FPGA-based systems-on-chip (SoC) including FPGA-based embedded processor SoCs. A SoC is a fully functional product having its electronic circuitry contained on a single chip. While a standalone microprocessor chip requires ancillary electronic components to process instructions, a SoC may include all required ancillary electronics on a single integrated circuit chip. For example, a SoC for a cellular telephone can include a microprocessor, encoder, decoder, digital signal processor (DSP), RAM and ROM. It should be understood when contemplating the present invention that an FPGA-Based SoC does not necessarily include a microprocessor or microcontroller. For example, a SoC for a cellular telephone could include an encoder, decoder, digital signal processor (DSP), RAM and ROM that rely on an external microprocessor. A SoC could also include multiple processing modules coupled to each other via a bus or several busses. It should also be understood herein that “FPGA-based embedded processor SoCs” are a specific subset of FPGA-based SoCs with or without their own processors.
The processing modules can either be hardware or software based.
Notwithstanding advantages provided by using FPGA-based SoCs, the development of these SoCs can be very challenging, particularly where software and hardware processing engines are combined in a single system. Existing systems for designing multiprocessors such as Coware SystemC cater to the needs of hardware designers with an emphasis on the detailed mechanics of a particular system. Such a system fails to allow a designer to work more in the software level of abstraction and fails to allow a user to use simple tags to implement different functions on different processing engines. In another system, the Celoxica Handel-C/Xilinx Forge compiler system allows C code to be translated directly into hardware using parallelizing compiler techniques. Rather than translating from C into hardware, there is a need to translate from function to structure where the structure can be hardware or software processors.
One of the other challenges includes communication among multiple hardware and software processors embedded in a FPGA-based SoC. Typically, such communication occurs over a bus. Unfortunately, communication over a bus involves a large amount of overhead due to bus arbitration times. Therefore, several clock cycles are typically needed for simple communication among processing modules. Furthermore, the actual links among the processing modules are not flexible in terms of defining or customizing data sizes and FIFO sizes. Also, many links among processors are processor type dependent. FPGA based embedded processor SoCs are being introduced into the market, but there are no solutions which allow users to customize the system, the hardware and software processing modules, the links among the processing modules, and the associated software, nor is there a system enabling a user to trade off a function between being implemented in hardware (FPGA fabric) or software (running on the embedded processor). It would be desirable to have a method and system for designing multiprocessor systems in FPGA-based SoCs that enables a translation (without resorting to a central processor or other co-processors) from function to structure including software and hardware processors independent of processing module type, and that further overcomes the shortcomings described above.